Generation Report - ALTMEMPHY v8.0 |
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Entity Name | altmemddr_phy_alt_mem_phy_siii | Variation Name | altmemddr_phy | Variation HDL | Verilog HDL | Output Directory | D:\NIOS_II\DE3_Q80\DE3_DDR2\DE3_DDR2_150 |
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File SummaryThe MegaWizard interface is creating the following files in the output directory: |
File | Description |
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altmemddr_phy.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. | altmemddr_phy.qip | Contains Quartus II project information for your MegaCore function variation. | altmemddr_phy.html | The MegaCore function report file. |
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MegaCore Function Variation File PortsName | Direction | Width |
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pll_ref_clk | INPUT | 1 | global_reset_n | INPUT | 1 | soft_reset_n | INPUT | 1 | reset_request_n | OUTPUT | 1 | phy_clk | OUTPUT | 1 | reset_phy_clk_n | OUTPUT | 1 | aux_half_rate_clk | OUTPUT | 1 | aux_full_rate_clk | OUTPUT | 1 | local_address | INPUT | 23 | local_read_req | INPUT | 1 | local_wdata | INPUT | 256 | local_write_req | INPUT | 1 | local_size | INPUT | 1 | local_be | INPUT | 32 | local_refresh_req | INPUT | 1 | local_burstbegin | INPUT | 1 | local_ready | OUTPUT | 1 | local_rdata | OUTPUT | 256 | local_rdata_valid | OUTPUT | 1 | local_init_done | OUTPUT | 1 | local_refresh_ack | OUTPUT | 1 | local_wdata_req | OUTPUT | 1 | ctl_address | OUTPUT | 23 | ctl_read_req | OUTPUT | 1 | ctl_wdata | OUTPUT | 256 | ctl_write_req | OUTPUT | 1 | ctl_size | OUTPUT | 1 | ctl_be | OUTPUT | 32 | ctl_refresh_req | OUTPUT | 1 | ctl_burstbegin | OUTPUT | 1 | ctl_ready | INPUT | 1 | ctl_wdata_req | INPUT | 1 | ctl_rdata | INPUT | 256 | ctl_rdata_valid | INPUT | 1 | ctl_refresh_ack | INPUT | 1 | ctl_mem_addr_h | INPUT | 13 | ctl_mem_addr_l | INPUT | 13 | ctl_mem_ba_h | INPUT | 2 | ctl_mem_ba_l | INPUT | 2 | ctl_mem_cas_n_h | INPUT | 1 | ctl_mem_cas_n_l | INPUT | 1 | ctl_mem_cke_h | INPUT | 1 | ctl_mem_cke_l | INPUT | 1 | ctl_mem_cs_n_h | INPUT | 1 | ctl_mem_cs_n_l | INPUT | 1 | ctl_mem_odt_h | INPUT | 1 | ctl_mem_odt_l | INPUT | 1 | ctl_mem_ras_n_h | INPUT | 1 | ctl_mem_ras_n_l | INPUT | 1 | ctl_mem_we_n_h | INPUT | 1 | ctl_mem_we_n_l | INPUT | 1 | ctl_mem_be | INPUT | 32 | ctl_mem_dqs_burst | INPUT | 1 | ctl_mem_wdata | INPUT | 256 | ctl_mem_wdata_valid | INPUT | 1 | ctl_mem_rdata | OUTPUT | 256 | ctl_mem_rdata_valid | OUTPUT | 1 | ctl_rlat | OUTPUT | 5 | ctl_init_done | INPUT | 1 | ctl_doing_rd | INPUT | 1 | ctl_add_1t_ac_lat | INPUT | 1 | ctl_add_1t_odt_lat | INPUT | 1 | ctl_add_intermediate_regs | INPUT | 1 | ctl_negedge_en | INPUT | 1 | ctl_usr_mode_rdy | OUTPUT | 1 | mem_addr | OUTPUT | 13 | mem_ba | OUTPUT | 2 | mem_cas_n | OUTPUT | 1 | mem_cke | OUTPUT | 1 | mem_cs_n | OUTPUT | 1 | mem_dm | OUTPUT | 8 | mem_odt | OUTPUT | 1 | mem_ras_n | OUTPUT | 1 | mem_we_n | OUTPUT | 1 | mem_reset_n | OUTPUT | 1 | mem_clk | BIDIR | 2 | mem_clk_n | BIDIR | 2 | mem_dq | BIDIR | 64 | mem_dqs | BIDIR | 8 | mem_dqsn | BIDIR | 8 | resynchronisation_successful | OUTPUT | 1 | postamble_successful | OUTPUT | 1 | tracking_successful | OUTPUT | 1 | tracking_adjustment_up | OUTPUT | 1 | tracking_adjustment_down | OUTPUT | 1 | dqs_delay_ctrl_import | INPUT | 6 | dqs_delay_ctrl_export | OUTPUT | 6 | dll_reference_clk | OUTPUT | 1 | pll_reconfig_enable | INPUT | 1 | pll_reconfig_counter_type | INPUT | 4 | pll_reconfig_counter_param | INPUT | 3 | pll_reconfig_data_in | INPUT | 9 | pll_reconfig_read_param | INPUT | 1 | pll_reconfig_write_param | INPUT | 1 | pll_reconfig | INPUT | 1 | pll_reconfig_clk | OUTPUT | 1 | pll_reconfig_reset | OUTPUT | 1 | pll_reconfig_data_out | OUTPUT | 9 | pll_reconfig_busy | OUTPUT | 1 | oct_ctl_rs_value | INPUT | 14 | oct_ctl_rt_value | INPUT | 14 | local_autopch_req | INPUT | 1 | local_powerdn_req | INPUT | 1 | local_self_rfsh_req | INPUT | 1 | local_self_rfsh_ack | OUTPUT | 1 | local_powerdn_ack | OUTPUT | 1 | ctl_autopch_req | OUTPUT | 1 | ctl_powerdn_req | OUTPUT | 1 | ctl_self_rfsh_req | OUTPUT | 1 | ctl_self_rfsh_ack | INPUT | 1 | ctl_powerdn_ack | INPUT | 1 |
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